continued understanding given PTX file and made plan on how to approach the transpiler part
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76
package/src/Transpiler.jl
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76
package/src/Transpiler.jl
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# culoadtest(N, rand(["add.f32", "sub.f32", "mul.f32", "div.approx.f32"]))
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function culoadtest(N::Int32, op = "add.f32")
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vadd_code = ".version 7.1
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.target sm_52
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.address_size 64
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// .globl VecAdd_kernel
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.visible .entry VecAdd_kernel(
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.param .u64 VecAdd_kernel_param_0,
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.param .u64 VecAdd_kernel_param_1,
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.param .u64 VecAdd_kernel_param_2,
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.param .u32 VecAdd_kernel_param_3
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)
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{
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.reg .pred %p<2>;
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.reg .f32 %f<4>;
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.reg .b32 %r<6>;
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.reg .b64 %rd<11>;
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ld.param.u64 %rd1, [VecAdd_kernel_param_0];
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ld.param.u64 %rd2, [VecAdd_kernel_param_1];
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ld.param.u64 %rd3, [VecAdd_kernel_param_2];
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ld.param.u32 %r2, [VecAdd_kernel_param_3];
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mov.u32 %r3, %ntid.x;
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mov.u32 %r4, %ctaid.x;
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mov.u32 %r5, %tid.x;
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mad.lo.s32 %r1, %r3, %r4, %r5;
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setp.ge.s32 %p1, %r1, %r2;
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@%p1 bra \$L__BB0_2;
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cvta.to.global.u64 %rd4, %rd1;
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mul.wide.s32 %rd5, %r1, 4;
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add.s64 %rd6, %rd4, %rd5;
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cvta.to.global.u64 %rd7, %rd2;
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add.s64 %rd8, %rd7, %rd5;
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ld.global.f32 %f1, [%rd8];
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ld.global.f32 %f2, [%rd6];" *
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op *
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" %f3, %f2, %f1;
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cvta.to.global.u64 %rd9, %rd3;
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add.s64 %rd10, %rd9, %rd5;
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st.global.f32 [%rd10], %f3;
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\$L__BB0_2:
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ret;
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}"
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linker = CuLink()
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add_data!(linker, "VecAdd_kernel", vadd_code)
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image = complete(linker)
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mod = CuModule(image)
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func = CuFunction(mod, "VecAdd_kernel")
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d_a = CUDA.fill(1.0f0, N)
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d_b = CUDA.fill(2.0f0, N)
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d_c = CUDA.fill(0.0f0, N)
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# Grid/Block configuration
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threadsPerBlock = 256;
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blocksPerGrid = (N + threadsPerBlock - 1) ÷ threadsPerBlock;
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@time CUDA.@sync cudacall(func, Tuple{CuPtr{Cfloat},CuPtr{Cfloat},CuPtr{Cfloat},Cint}, d_a, d_b, d_c, N; threads=threadsPerBlock, blocks=blocksPerGrid)
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end
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