Daniel
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  • Joined on 2023-09-27
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Daniel pushed to main at Daniel/master-thesis 2025-01-25 11:16:06 +01:00
7598c51df8 finished generating parameter loading code
Daniel pushed to main at Daniel/master-thesis 2025-01-24 13:14:02 +01:00
b2774322a1 added loading of variables from memory into registers. Note: Needed to leave, so code currently not compiling
Daniel pushed to main at Daniel/master-thesis 2025-01-19 11:00:48 +01:00
85464083c3 aded symtable for loading vars and params to local memory
Daniel pushed to main at Daniel/playaround_ideas 2025-01-12 10:25:09 +01:00
d60e78f47a Initial ideas
Daniel created repository Daniel/playaround_ideas 2025-01-12 10:21:45 +01:00
Daniel pushed to main at Daniel/master-thesis 2025-01-06 14:02:05 +01:00
219c0bb14e started implementing parameter loading
Daniel pushed to main at Daniel/master-thesis 2025-01-05 11:19:13 +01:00
f7926c3438 finished implementing operators
Daniel pushed to main at Daniel/master-thesis 2025-01-04 10:40:36 +01:00
094f8c9499 Merge branch 'main' of https://github.com/daniwipes/master-thesis
a97b804530 testing interpreter because loop seems to do everything. Can't test right now because I don't have a nvidia gpu in my laptop
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Daniel pushed to main at Daniel/master-thesis 2025-01-04 10:38:37 +01:00
9702fe2343 added thesis structure
Daniel opened issue Daniel/master-thesis#10 2024-12-11 10:53:13 +01:00
Interpreter index calculation
Daniel pushed to main at Daniel/master-thesis 2024-12-10 22:58:32 +01:00
8d129dbfcc rewrote function for generating code for operators. now the entire operation will be returned and not just the operator
Daniel pushed to main at Daniel/master-thesis 2024-12-08 10:50:26 +01:00
67ef9a5139 reworked code to use new 'register manager'
Daniel pushed to main at Daniel/master-thesis 2024-12-07 10:23:27 +01:00
203900bb26 nevermind, improved register management worked
Daniel pushed to main at Daniel/master-thesis 2024-12-07 10:13:14 +01:00
1e7f6e9010 tried streamlining register management
Daniel pushed to main at Daniel/master-thesis 2024-11-01 11:24:04 +01:00
68cedd75fc updated all to 32-bit to save registers and boost performance
Daniel pushed to main at Daniel/master-thesis 2024-10-27 11:48:29 +01:00
9fc55c4c15 started implementing transpilation of expression
Daniel pushed to main at Daniel/master-thesis 2024-10-26 11:41:19 +02:00
0e24d74e54 small increment and fixes
Daniel pushed to main at Daniel/master-thesis 2024-10-20 12:24:26 +02:00
ee3c5001bd added information on how to best approach register assignment
Daniel commented on issue Daniel/master-thesis#9 2024-10-20 12:12:59 +02:00
Interesting papers

Things that might be interesting for Related Work:

Register Allocation/Assignment (maybe even for interpretors?)

Daniel pushed to main at Daniel/master-thesis 2024-10-19 13:44:49 +02:00
1f6b40b750 added possibility to create registers